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? 2002 microchip technology inc. ds21433b-page 1 tc530/TC534 features ? precision (up to 17-bits) a/d converter 3-wireserialport flexible: user can trade off conversion speed for resolution single supply operation -5voutputpin 4 input, differential analog mux (TC534) automatic input polarity and overrange detection low operating current: 5ma max wide analog input range: 4.2v max cost effective applications precision analog signal processor precision sensor interface high accuracy dc measurements device selection table package types part number package temperature range tc530coi 28-pin soic 0c to +70c tc530cpj 28-pin pdip (narrow) 0c to +70c TC534ckw 44-pin pqfp 0c to +70c TC534cpl 40-pin pdip 0c to +70c 1 2 3 4 20 19 18 5 6 7 8 17 23 22 21 9 10 11 12 24 25 26 27 28 tc530cpi tc530coi 16 15 13 14 v ss c ref - c ref + v ref - v ref + c int c az buf acom osc out v in - v in + dgnd n/c v ccd v dd d out d clk cap- agnd reset nc osc cap+ osc in d in r/w eoc 28-pin soic 28-pin pdip v cdd v dd osc out cap- cap+ osc in d out d clk d in ch2+ ch3+ ch1+ dgnd agnd a1 a0 27 26 25 24 23 7 8 9 10 11 nc nc 12 13 14 15 16 17 18 19 20 21 22 38 37 36 35 34 nc 39 40 41 42 43 44 28 29 30 31 32 33 6 5 4 3 2 1 buf c az v ss c int nc nc nc osc reset nc nc nc eoc nc r/w TC534ckw 44-pin pqfp ch4+ ch4- ch3- ch2- ch1- c ref - c ref + v ref - v ref + acom v dd dgnd v ccd cap- agnd osc n/c n/c n/c cap+ TC534cpl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a1 a0 n/c n/c n/c ch1+ ch2+ ch3+ ch4+ ch4- ch3- ch2- ch1- 40-pin pdip v ss c ref - c ref + v ref - v ref + c int c az buf acom d out d clk reset osc in osc out d in r/w eoc 5v precision data acquisition subsystems
tc530/TC534 ds21433b-page 2 ? 2002 microchip technology inc. general description the tc530/TC534 are serial analog data acquisition subsystems ideal for high precision measurements (up to 17-bits plus sign). the tc530 consists of a dual slope integrating a/d converter, negative power sup- ply generator and 3 wire serial interface port. the TC534 is identical to the tc530, but adds a four chan- nel differential input multiplexer. key a/d converter operating parameters (auto zero and integration time) are programmable, allowing the user to trade conversion time for resolution. data conversion is initiated when the reset input is brought low. after conversion, data is loaded into the output shift register and eoc is asserted, indicating new data is available. the converted data (plus over- range and polarity bits) is held in the output shift regis- ter until read by the processor or until the next conversion is completed, allowing the user to access data at any time. the tc530/TC534 timebase can be derived from an external crystal of 2mhz (max) or from an external fre- quency source. the tc530/TC534 requires a single 5v power supply and features a -5v, 10ma output which can be used to supply negative bias to other components in the system. typical application a0 a1 osc in r/w d in d out d clk osc out osc reset cap+ cap? c az tc530 TC534 c ref r int c int TC534 (only) ( tc530 only) dc-to-dc converter state machine serial port negative supply output oscillator ( 4) dual slope a/d converter .01 f 0.01 f optional power-on reset ca p 100k +5v dif. mux ( TC534 only) ab cmptr buf int c az acom v dd v dd v dd v dd v ss mcp1525 v ref - v ref + v in - v in + eoc ch2+ ch3+ ch1+ ch4+ ch4- ch3- ch2- ch1- in+ in- c ref - c ref +
? 2002 microchip technology inc. ds21433b-page 3 tc530/TC534 1.0 electrical characteristics absolute maximum ratings* supply voltage ...................................................... +6v analog input voltage (v in +orv in -).............v dd to v ss logic input voltage......... (v dd + 0.3v) to (gnd - 0.3v) ambient operating temperature range: pdip package (c)................. 0c to +70c soic package (c) ................ 0c to +70c pqfp package (c) ............... 0c to +70c storage temperature range .............. -65c to +150c *stresses above those listed under "absolute maximum rat- ings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. expo- sure to absolute maximum rating conditions for extended periods may affect device reliability. tc530/tc530a/TC534 electrical specifications electrical characteristics: v dd =v ccd ,c az =c ref =0.47 f, unless otherwise specified. symbol parameter t a =+25c t a =0cto+70c unit test conditions min typ max min typ max v dd analog power supply voltage 4.5 5.0 5.5 4.5 ? 5.5 v v ccd digital power supply voltage 4.5 5.0 5.5 4.5 ? 5.5 v p d tc530/TC534 total power dissipation ??25 ? ??m ? v dd =v ccd =5v i s supply current (v s +p in )?1.82.5??3.0ma i ccd supply current (v ccd p in )??1.5 ??1.7maf osc =1mhz analog r resolution ? ? 17 ? ? 17 bits note 1 zse zero scale error with auto zero phase ? ? 0.5 ? 0.005 0.012 % f.s. enl end point linearity ? 0.015 0.030 ? 0.015 0.045 % f.s. note 1 and note 2 nl max. deviation from best straight line fit ? 0.008 0.015 ? ? ? % f.s. note 1 and note 2 zs tc zero scale temperature coefficient ??? ? 1 2v/c sye rollover error ? .012 ? ? .03 ? % f.s. note 3 fs tc full scale temperature coefficient ? ? ? ? 10 ? ppm/ c ext. v ref t.c . = 0 pp m /c i in input current ? 6 ? ? ? ? pa v in =0v v cmr common-mode voltage range v ss +1.5 ? v dd -1.5 v ss +1.5 ? v dd -1.5 v v int integrator output swing v ss +0.9 ? v dd -0.9 v ss +0.9 ? v dd -0.9 v v in analog input signal range v ss +1.5 ? v dd -1.5 v ss +1.5 ? v dd -1.5 v v ref voltage reference range v ss +1 ? v dd -1 v dd +1 ? v dd -1 v t d zero crossing comparator delay ?2.0? ? 3.0? sec note 1: integrate time 66msec, auto zero time 66msec, v int (pk) = 4v. 2: end point linearity at 1/4, 1/2 3/4, f.s. after full scale adjustment. 3: rollover error is related to capacitor used for c int . see table 5-2, recommended capacitor for c int . 4: TC534 only.
tc530/TC534 ds21433b-page 4 ? 2002 microchip technology inc. serial port interface v ih input logic high level 2.5 ? ? 2.5 ? ? v v il input logic low level ? ? 0.8 ? ? 0.8 v i in input current (di, do, d clk ) ??10 ? ? ? a v ol logic low output voltage (eoc ) ? 0.2 0.3 ? ? 0.35 v i out =250 a t r ,t f rise and fall times (eoc ,di,do) ??250 ? 250 nsecc l =10pf f xtl crystal frequency ? ? 2.0 ? ?2.0mhz f ext external frequency on osc in ??4.0 ? ?4.0mhz t rs read setup time 1 ? ? ? 1 ? sec t rd read delay time 250 ? ? ? 250 nsec t drs d clk to d out delay 450 ? ? ? 450 nsec t pwl d clk low pulse width 150 ? ? ? 150 nsec t pwh d clk high pulse width 150 ? ? ? 150 nsec t dr data ready delay 200 ? ? ? 200 nsec r out output resistance ? 65 85 ? ? 100 ? i out =10ma f clk oscillator frequency ? 100 ? ? ? ? khz c osc =0 i out v ss output current ? ? 10 ? ? 10 ma multiplexer v immax maximum input voltage -2.5 ? 2.5 -2.5 ? 2.5 v r dson drain/source on resistance ? 6 10 ? ? ? k ? tc530/tc530a/TC534 electrical specifications (continued) electrical characteristics: v dd =v ccd ,c az =c ref =0.47 f, unless otherwise specified. symbol parameter t a =+25c t a =0cto+70c unit test conditions min typ max min typ max note 1: integrate time 66msec, auto zero time 66msec, v int (pk) = 4v. 2: end point linearity at 1/4, 1/2 3/4, f.s. after full scale adjustment. 3: rollover error is related to capacitor used for c int . see table 5-2, recommended capacitor for c int . 4: TC534 only.
? 2002 microchip technology inc. ds21433b-page 5 tc530/TC534 2.0 pin descriptions thedescriptionsofthepinsarelistedintable2-1 table 2-1: pin function table pin number ( tc530 ) 28-pin pdip pin number ( tc530 ) 28-pin soic pin number ( TC534 ) 40-pin pdip pin number ( TC534 ) 44-pin pqfp symbol description 11 140v ss analog output. negative power supply converter output and reservoir capacitor connection. this output can be used to provide negative bias to other devices in the system. 22 241c int analog output. integrator capacitor connection and integrator output. 33 342c az analog input. auto zero capacitor connection. 4 4 4 43 buf analog output. integrator capacitor connection and voltage buffer output. 5 5 5 2 acom analog input. this pin is ground for all of the analog switches in the a/d converter. it is grounded for most applications. acom and the input common pin (v in -or chx-) should be within the common mode range, cmr. 66 6 3c ref - analog input. reference cap negative connection. 77 7 4c ref + analog input. reference cap positive connection. 88 8 5v ref - analog input. external voltage reference negative connec- tion. 99 9 6v ref + analog input. external voltage reference positive connec- tion. not used not used 10 7 ch4- analog input. multiplexer channel 4 negative differential not used not used 11 8 ch3- analog input. multiplexer channel 3 negative differential not used not used 12 9 ch2- analog input. multiplexer channel 2 negative differential not used not used 13 10 ch1- analog input. multiplexer channel 1 negative differential not used not used 14 11 ch4+ analog input. multiplexer channel 4 positive differential not used not used 15 12 ch3+ analog input. multiplexer channel 3 positive differential not used not used 16 13 ch2+ analog input. multiplexer channel 2 positive differential not used not used 17 14 ch1+ analog input. multiplexer channel 1 positive differential 10 10 not used not used v n - analog input. negative differential analog voltage input. 11 11 not used not used v in + analog input. positive differential analog voltage input. 12 12 18 15 dgnd analog input. ground connection for serial port circuit. not used not used 19 16 a1 logic level input. multiplexer address msb. not used not used 20 17 a0 logic level input. multiplexer address lsb. 14 14 21 18 osc out analog input. timebase for state machine. this pin con- nects to one side of an at-cut crystal having an effective series resistance of 100 ? (typ) and a parallel capacitance of 20pf. if an external frequency source is used to clock the tc530/TC534 this pin must be left floating. 15 15 22 19 osc in analog input. this pin connects to the other side of the crys- tal described in osc out above. the tc530/TC534 may also be clocked from an external frequency source con- nected to this pin. the external frequency source must be a pulse wave form with a minimum 30% duty cycle and rise and fall times 15nsec (max). if an external frequency source is used, osc out must be left floating. a maximum operat- ing frequency of 2mhz (crystal) or 4mhz (external clock source) is permitted.
tc530/TC534 ds21433b-page 6 ? 2002 microchip technology inc. 16 16 23 20 d out logic level output. serial port data output pin. this pin is enabled only when r/w is high. 17 17 24 21 d clk logic input, positive and negative edge triggered. serial port clock. when r/w is high, serial data is clocked out of the tc530/TC534a (on d out ) at each high-to-low transition of d clk . a/d initialization data (load value) is clocked into the tc530/TC534 (on d in ) at each low-to-high transi- tion of d clk .amaximumserialportd clk frequency of 3mhz is permitted. 18 18 25 22 d in logic level input. serial port input pin. the a/d converter integration time (t int ) and auto zero time (t az ) values are determined by the load value byte clocked into this pin. this initialization must take place at power up, and can be rewritten (or modified and rewritten) at any time. the load value is clocked into d in msb first. 19 19 26 23 r/w logic level input. this pin must be brought low to perform a write to the serial port (e.g. initialize the a/d converter). the d out pin of the serial port is enabled only when this pin is high. 20 20 27 24 eoc open drain output. end-of-conversion (eoc )isasserted any time the tc530/TC534 is in the az phase of conver- sion. this occurs when either the tc530/TC534 initiates a normal az phase or when reset is pulled high. eoc is returned high when the tc530/TC534 exits az. since eoc is driven low immediately following completion of a conver- sion cycle, it can be used as a data ready processor interrupt. 21 21 30 28 reset logic level input. it is necessary to force the tc530/TC534 into the auto zero phase when power is initially applied. this is accomplished by momentarily taking reset high. using an i/o port line from the microprocessor or by apply- ing an external system reset signal or by connecting a 0.01 f capacitor from the reset input to v dd .conver- sions are performed continuously as long as reset is low and conversion is halted when reset is high. reset may therefore be used in a complex system to momentarily sus- pend conversion (for example, while the address lines of an input multiplexer are changing state). in this case, reset should be pulled high only when the eoc is low to avoid excessively long integrator discharge times which could result in erroneous conversion. (see applications section). 22 22 32 30 v ccd analog input. power supply connection for digital logic and serial port. proper power-up sequencing is critical, see the applications section. 23 23 34 32 osc input. the negative power supply converter normally runs at a frequency of 100khz. this frequency can be slowed down to reduce quiescent current by connecting an external capacitor between this pin and v + dd. see section 6.0, typical characteristics. 25 25 37 35 v dd analog input. power supply connection for the a/d analog section and dc-dc converter. proper power-up sequencing is critical, (see the applications section). table 2-1: pin function table (continued) pin number ( tc530 ) 28-pin pdip pin number ( tc530 ) 28-pin soic pin number ( TC534 ) 40-pin pdip pin number ( TC534 ) 44-pin pqfp symbol description
? 2002 microchip technology inc. ds21433b-page 7 tc530/TC534 26 26 38 36 cap+ analog input. storage capacitor positive connection for the dc/dc converter. 27 27 39 37 agnd analog input. ground connection for dc/dc converter. 28 28 40 38 cap- analog input. storage capacitor negative connection for the dc/dc converter. 13, 24 13, 24 28, 29, 31, 33, 35, 36 1, 25, 26, 27, 29, 31, 33, 34, 39, 44 nc no connect. do not connect any signal to these pins. table 2-1: pin function table (continued) pin number ( tc530 ) 28-pin pdip pin number ( tc530 ) 28-pin soic pin number ( TC534 ) 40-pin pdip pin number ( TC534 ) 44-pin pqfp symbol description
tc530/TC534 ds21433b-page 8 ? 2002 microchip technology inc. 3.0 detailed description 3.1 dual slope integrating converter the tc530/TC534 dual slope converter operates by integrating the input signal for a fixed time period, then applying an opposite polarity reference voltage while timing the period (counting clocks pulses) for the inte- grator output to cross 0v (deintegrating). the resulting count is read as conversion data. a simple mathematical expression that describes dual slope conversion is: equation 3-1: equation 3-2: from which: equation 3-3: and therefore: equation 3-4: inspection of equation 3-4 shows dual slope converter accuracy is unrelated to integrating resistor and capac- itor values, as long as they are stable throughout the measurement cycle. this measurement technique is inherently ratiometric (i.e., the ratio between the t int and t deint times is equal to the ratio between v in and v ref ). another inherent benefit is noise immunity. input noise spikes are integrated, or averaged to zero, during the integration period. the integrating converter has a noise immunity with an attenuation rate of at least -20db per decade. interference signals with frequencies at integral multiples of the integration period are, for the most part, completely removed. for this reason, the integration period of the converter is often established to reject 50/ 60hz line noise. the ability to reject such noise is shown bytheplotoffigure3-1. in addition to the two phases required for dual slope measurement (integrate and de-integrate), the tc530/ TC534 performs two additional adjustments to minimize measurement error due to system offset volt- ages. the resulting four internal operations (conver- sion phases) performed each measurement cycle are: auto zero (az), integrator output zero (iz), input inte- grate (int) and reference de-integrate (dint). the az and iz phases compensate for system offset errors and the int and dint phases perform the actual a/d conversion. figure 3-1: integrating converter normal mode rejection 3.2 auto zero phase (az) this phase compensates for errors due to buffer, inte- grator and comparator offset voltages. during this phase, an internal feedback loop forces a compensat- ing error voltage on auto zero capacitor (c az ). the duration of the az phase is programmable via the serial port (see section 4.1.1, az and int phase duration). integrate voltage = de-integrate voltage 1 r int c int t int 0 v in (t)dt = 1 r int c int t deint 0 v ref (v in ) (r int )(c int ) [ (t int ) =(v ref ) ] (r int )(c int ) [ (t deint ) ] v in =v ref [ ] t int t deint where: v ref = reference voltage t int =integratetime t deint = reference voltage de-integrate time 30 20 10 0 0.1/t 1/t 10/t input frequenc y normal mode rejection (db) t = measurement period
? 2002 microchip technology inc. ds21433b-page 9 tc530/TC534 figure 3-2: serial port timing figure 3-3: a/d converter timing 3.3 input integrate phase (int) in this phase, a current directly proportional to differen- tial input voltage is sourced into integrating capacitor c int . the amount of voltage stored on c int at the end of the int phase is directly proportional to the applied differential input voltage. input signal polarity (sign bit) is determined at the end of this phase. converter resolution and speed is a function of the duration of the int phase, which is programmable by the user via the serial port (see section 4.1.1, az and int phase dura- tion). the shorter the integration time, the faster the speed of conversion (but the lower the resolution). conversely, the longer the integration time, the greater the resolution (but at slower the speed of conversion). t rd t rs t drs t pwl r/w read timing read format write format write timing write default timing eoc d out d clk r/w eoc d out d clk eoc sgn msb lsb ovr t ls t dls t pwl r/w d in d clk t ldl t lds d in r/w d out d clk msb lsb for polled vs interrupt operation and write value modified cycle use tc520a data sheet (ds21431). r/w eoc t dr az updated data ready updated data ready int dint iz az conversion phase data to serial port transmit register
tc530/TC534 ds21433b-page 10 ? 2002 microchip technology inc. 3.4 reference de-integrate phase (dint) this phase consists of measuring the time for the inte- grator output to return (at a rate determined by the external reference voltage) from its initial voltage to 0v. the resulting timer data is stored in the output shift reg- ister as converted analog data. 3.5 integrator output zero phase (iz) this phase ensures the integrator output is at zero volts when the az phase is entered so that only true system offset voltages will be compensated for. all internal converter timing is derived from the fre- quency source at osc in and osc out . this frequency source must be either an externally provided clock signal or an external crystal. if an external clock is used, it must be connected to the osc in pin and the osc out pin must remain floating. if a crystal is used, it must be connected between osc in and osc out and be physically located as close to the osc in and osc out pins as possible. in either case, the incoming clock frequency is divided by four, with the resulting clock serving as the internal tc530/TC534 timebase. 4.0 typical applications 4.1 programming the tc530/TC534 4.1.1 az and int phase duration these two phases have equal duration determined by the crystal (or external) frequency and the timer initial- ization byte (load value). timing is selected as follows: 1. select integration time integrationtimemustbepickedasamultipleofthe period of the line frequency. for example, t int times of 33msec, 66msec and 132msec maximize 60hz line rejection. 2. estimate crystal frequency crystal frequencies as high as 2mhz are allowed. crystal frequency is estimated using: equation 4-1: 3. calculate load value equation 4-2: f in can be adjusted to a standard value during this step. the resulting base, -10 load value, must be converted to a hexadecimal number and then loaded into the serial port prior to initiating a/d conversion. 4.2 dint and iz phase timing the duration of the dint phase is a function of the amount of voltage stored on the integrator capacitor during int and the value of v ref . the dint phase is ini- tiated immediately following int and terminated when an integrator output zero crossing is detected. in gen- eral, the maximum number of counts chosen for dint is twicethatofint(withv ref chosen at v in(max) /2). 4.3 system reset the tc530/TC534 must be forced into the az state when power is first applied. a .01 f capacitor con- nected from reset to v dd (or external system reset logic signal) can be used to momentarily drive reset high for a minimum of 100msec. 4.4 design example figure 4-1 shows a typical TC534 interrupt-driven application. timing and component values are calcu- lated from equations and recommendations made in section 3.1 and section 4.1 of this document. the eoc connection to the processor int input is for inter- rupt-driven applications only. (in polled systems, the eoc output is available on d out ). given: required resolution:16-bits (65,536 counts.) maximum: v in 2v power supply voltage: +5v 60hz system 1. pick integration time (t int ): 66msec 2. estimate crystal frequency. example 4-1: 3. calculate load value example 4-2: 2(r)/t int where: r = desired converter resolution (in counts) f in = input frequency (in mhz) int = integration time (in seconds) 256 - (t int )(f in ) [load value]10 = 1024 f in =2r/t int = 2 x 65536/66 x 10 -3 =1.98mhz (use 2mhz) load value = 256 ? (t int )(f in )/1024 = [128] 10 [128] 10 = 80 hex
? 2002 microchip technology inc. ds21433b-page 11 tc530/TC534 4. calculate r int example 4-3: 5. calculate c int for maximum (4v) integrator out- put swing: example 4-4: note: microchip recommended capacitor: evox-rifa p/n: smr5 334k50j03l 6. choose c ref and c az based on conversion rate: example 4-5: note: microchip recommended capacitor: evox-rifa p/n: smr5 224k50j02l4 7. calculate v ref . example 4-6: 4.5 power supply sequencing improper sequencing of the power supply inputs (v dd vs. v ccd ) can potentially cause an improper power-up sequence to occur. see section 4.6, circuit design/ layout considerations. failing to insure a proper power-up sequence can cause spurious operation. 4.6 circuit design/layout considerations 1. separate ground return paths should be used for the analog and digital circuitry. use of ground planes and trace fill on analog circuit sections is highly recommended except for in and around the integrator section and c ref ,c az (c int , c ref ,c az ,r int ). stray capacitance between these nodes and ground appears in parallel with the components themselves and can affect measurement accuracy. 2. improper sequencing of the power supply inputs (v dd vs. v ccd ) can potentially cause an improper power-up sequence to occur in the internal state machines. it is recommended that the digital supply, v ccd , be powered up first. one method of insuring the correct power-up sequence is to delay the analog supply using a series resistor and a capacitor. see figure 4-1, tc530/TC534 typical application. 3. decoupling capacitors, preferably a higher value electrolytic or tantulum in parallel with a small ceramic or tantalum, should be used liber- ally. this includes bypassing the supply connec- tions of all active components and the voltage reference. 4. critical components should be chosen for stabil- ity and low noise. the use of a metal-film resistor for r int and polypropylene or polyphenelyne sulfide (pps) capacitors for c int ,c az and c ref is highly recommended. 5. the inputs and integrator section are very high impedance nodes. leakage to or from these crit- ical nodes can contribute measurement error. a guard-ring should be used to protect the integra- tor section from stray leakage. 6. circuit assemblies should be exceptionally clean to prevent the presence of contamination from assembly, handling or the cleaning itself. minute conductive trace contaminates, easily ignored in most applications, can adversely affect the performance of high impedance cir- cuits. the input and integrator sections should be made as compact and close to the tc53x as possible. 7. digital and other dynamic signal conductors should be kept as far from the tc53x?s analog section as possible. the microcontroller or other host logic should be kept quiet during a mea- surement cycle. background activities such as keypad scanning, display refreshing and power switching can introduce noise. r int =v inmax /20 = 2/20 = 100k ? c int =(t int )(20 x 10 ?6 )/ (v s ?0.9) = (.066)(20 x 10 ?6 )/(4.1) =.32 f (use closest value: 0.33 f) conversions/sec = 1/(t az +t int +2t int +2msec) = 1/(66msec + 66msec + 132msec + 2msec) = 3.7 conversions/sec from which c az =c ref =0.22 f (table 5-1) (v s ?0.9)(c int )(r int ) v ref = 2(t int ) =(4.1)(0.33x1 ?6 )(10 5 ) / 2(.066) = 1.025v
tc530/TC534 ds21433b-page 12 ? 2002 microchip technology inc. figure 4-1: tc530/TC534 typical application a0 a1 reset v ccd v ccd v dd v dd d out d clk x1: 2mhz r2 100k r1 100k 100 ? 1 f (1.03v) d in r/w acom osc in osc out v ss dgnd c az c az 0.22 f c in 0.33 f r int 100k TC534 c int analog inputs channel control c1 .01 f 10 f mux in1+ in1- in2+ in2- in3+ in3- in4+ in4- +5v +5v ? 5v (optional) buf c ref 0.22 f 1 f +5v eoc int processor i/o i/o i/o i/o .01 f .01 f 1 f cap- cap+ c ref - c ref + v ref - v ref +
? 2002 microchip technology inc. ds21433b-page 13 tc530/TC534 5.0 selecting component values for the tc530/TC534 1. calculate integrating resistor ( r int ) the desired full scale input voltage and amplifier output current capability determine the value of r int . the buffer and integrator amplifiers each have a full scale current of 20 a. the value of r int is therefore directly calculated as follows: equation 5-1: 2. select reference (c ref ) and auto zero (c az ) capacitors c ref and c az must be low leakage capacitors (such as polypropylene). the slower the conver- sion rate, the larger the value c ref must be. rec- ommended capacitors for c ref and c az are shown in table 5-1. larger values for c az and c ref mayalsobeusedtolimitrollovererrors. table 5-1: c ref and c az selection 5.1 calculate integrating capacitor (c int ) the integrating capacitor must be selected to maximize integrator output voltage swing. the integrator output voltage swing is defined as the absolute value of v dd (or v ss ) less 0.9v (i.e.,iv dd ? 0.9vi or iv ss +0.9vi). using the 20 a buffer maximum output current, the value of the integrating capacitor is calculated using the following equation. equation 5-2: it is critical that the integrating capacitor have a very low dielectric absorption. pps capacitors are an exam- ple of one such dielectric. table 5-2 summarizes various capacitors suitable for c int . table 5-2: recommended capacitor for c int 5.2 calculate v ref the reference de-integration voltage is calculated using the following equaton: equation 5-3: 5.3 serial port communication with the tc530/TC534 is accom- plished over a 3 wire serial port. data is clocked into d in on the rising edge of d clk and clocked out of d out on the falling edge of d clk .r/w must be high to read converted data from the serial port and low to write the load value to the tc530/TC534. 5.4 data read cycle data is shifted out of the serial port in the following order: end of conversion (eoc ), overrange (ovr), polarity (pol), conversion data (msb first). when r/w is high, the state of the eoc bit can be polled by simply reading the state of d out . this allows the processor to determine if new data is available without connecting an additional wire to the eoc output pin (this is espe- cially useful in a polled environment). see figure 5-1. figure 5-1: serial port data read cycle conversion per second typical value of c ref ,c az ( f) suggested * part number >7 0.1 smr5 104k50j0il 2 to 7 0.22 smr5 224k50j2l 2 or less 0.47 smr5 474k50j04l note: * manufactured by evox-rifa, inc. v inmax 20 r int = m ? where: v in(max) = maximum input voltage (full count voltage) r int = integrating resistor (in m ? ) for loop stability, r int should be 50k ? . (t int )(20x10 -6 ) (v s -0.9) c int = f where: t int = integration period v s =iv dd i c int = integrated capacitor value ( f). value ( f) suggested part number* 0.1 smr5 104k50j0il 0.22 smr5 224k50j2l 0.33 smr5 334k50j03l4 0.47 smr5 474k50j04l note: * manufactured by evox-rifa, inc. (v s ?0.9)(c int )(r int ) v ref = 2(r int ) v eoc ovr pol msb lsb r/w d clk d out
tc530/TC534 ds21433b-page 14 ? 2002 microchip technology inc. 5.5 load value write cycle following the power-up reset pulse, the load value (which sets the duration of az and int) must next be transmitted to the serial port. to accomplish this, the processor monitors the state of eoc (which is available as a hardware output or at d out ). r/w is taken low to initiate the write cycle only when eoc is low (during the az phase). (failure to observe eoc low may cause an offset voltage to be developed across c int , resulting in erroneous readings). the 8-bit load value data on d in isclockedinbyd clk . the processor then termi- nates the write cycle by taking r/w high. (data is transferred from the serial input shift register to the time base counter on the rising edge of r/w and data conversion is initiated). see figure 5-2. 5.6 input multiplexer ( TC534 only) a 4-input, differential multiplexer is included in the TC534. the states of channel address lines a0 and a1 determine which differential v in pair is routed to the converter input. a0 is the least significant address bit (i.e., channel 1 is selected when a0 = 0 and a1 = 0). the multiplexer is designed to be operated in a differ- ential mode. for single-ended inputs, the chx- input for the channel under selection must be connected to the ground reference associated with the input signal. figure 5-2: tc530/TC534 initialization and load value write cycle 5.7 dc/dc converter an on-board, tc7660h-type charge pump supplies negative bias to the converter circuitry, as well as to external devices. the charge pump develops a nega- tive output voltage by moving charge from the power supply to the reservoir capacitor at v ss by way of the commutating capacitor connected to the cap+ and cap- inputs. the charge pump clock operates at a typical frequency of 100khz. if lower quiescent current is desired, the charge pump clock can be slowed by connecting an external capacitor from the osc pin to v dd . reference typical characteristics curves. eoc r/w reset d clk d in 1 1001111 az az load value msb lsb int dint iz az ? conversion phase timing status converter held in az state due to reset = 1 write load value to serial port power-up reset undefined converter in normal service r/w brought low during az for serial port write cycle r/w = high strobes load value into timebase and starts conversion continuous conversions
? 2002 microchip technology inc. ds21433b-page 15 tc530/TC534 6.0 typical characteristics the graphs and tables following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range), and therefore outside the warranted range. load current (ma) -5 -4 -3 -2 -1 0 1 2 3 4 5 010203040 50 60 70 80 output voltage (v) output voltage vs. load current t a = 25 ? c v+ = 5v slope 60 ? load current (ma) 0 3 456 12 78 910 0 25 50 75 100 125 150 175 200 output ripple (mv pk-pk) output ripple vs. load current v+ = 5v, t a = 25?c osc. freq. = 100khz cap = 1 f cap = 10 f oscillator capacitance (pf) 100 10 1 110 100 1000 oscillator frequency (khz) oscillator frequency vs. capacitance t a = +25 ? c v+ = 5v output current (ma) 06810 4 2141618 12 20 -0 -1 -3 -2 -4 -5 -7 -6 -8 output voltage vs. output current t a = 25 ? c output voltage (v) temperature ( ? c) 70 80 90 100 60 50 40 -50 025 -25 50 75 100 output source resistance ( ? ) output source resistance vs. temperature v+ = 5v i out = 10ma temperature ( ? c ) 125 150 100 75 50 -50 025 -25 50 75 125 100 oscillator frequency (khz) oscillator frequency vs. temperature v+ = 5v
tc530/TC534 ds21433b-page 16 ? 2002 microchip technology inc. 7.0 packaging information 7.1 package marking information package marking data not available at this time. 7.2 taping forms component taping orientation for 28-pin soic (wide) devices pin 1 user direction of feed standard reel component orientation for tr suffix device w p package carrier width (w) pitch (p) part per full reel reel size 28-pin soic (w) 24 mm 12 mm 1000 13 in carrier tape, number of components per reel and reel size component taping orientation for 44-pin pqfp devices w user direction of feed pin 1 standard reel component orientation for tr suffix device p package carrier width (w) pitch (p) part per full reel reel size 44-pin pqfp 24 mm 16 mm 500 13 in carrier tape, number of components per reel and reel size note: drawing does not represent total number of pins.
? 2002 microchip technology inc. ds21433b-page 17 tc530/TC534 7.3 package dimensions pin 1 3 ? min. 28-pin pdip (narrow) 1.400 (35.56) 1.345 (34.16) .022 (0.56) .015 (0.38) .110 (2.79) .090 (2.29) .070 (1.78) .045 (1.14) .150 (3.81) .115 (2.92) .045 (1.14) .030 (0.76) .288 (7.32) .240 (6.10) .200 (5.08) .140 (3.56) .015 (0.38) .008 (0.20) .400 (10.16) .310 (7.87) .310 (7.87) .290 (7.37) .040 (1.02) .015 (0.38) dimensions: inches (mm) 2.065 (52.45) 2.027 (51.49) .200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .022 (0.56) .015 (0.38) .110 (2.79) .090 (2.29) .555 (14.10) .530 (13.46) .610 (15.49) .590 (14.99) .015 (0.38) .008 (0.20) .700 (17.78) .610 (15.50) .040 (1.02) .020 (0.51) 40-pin pdip (wide) pin 1 3 ? min. dimensions: inches ( mm )
tc530/TC534 ds21433b-page 18 ? 2002 microchip technology inc. 7.3 package dimensions (continued) .299 (7.59) .291 (7.40) .103 (2.62) .097 (2.46) 8 ? max. .713 (18.11) .697 (17.70) .019 (0.48) .014 (0.36) .419 (10.65) .398 (10.10) pin 1 .050 (1.27) .016 (0.40) .013 (0.33) .009 (0.23) .012 (0.30) .004 (0.10) 28-pin soic (wide) dimensions: inches ( mm ) .557 (14.15) .537 (13.65) .398 (10.10) .390 (9.90) .031 (0.80) typ. .018 (0.45) .012 (0.30) .398 (10.10) .390 (9.90) .010 (0.25) typ. .096 (2.45) max. .557 (14.15) .537 (13.65) .083 (2.10) .075 (1.90) .041 (1.03) .026 (0.65) 7 ? max. .009 (0.23) .005 (0.13) 44-pin pqfp pin 1 dimensions: inches ( mm )
? 2002 microchip technology inc. ds21433b-page 19 tc530/534 sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
tc530/534 ds21433b-page 20 ? 2002 microchip technology inc. notes:
? 2002 microchip technology inc. ds21433b-page 21 tc530/TC534 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, filterlab, k ee l oq ,microid, mplab,pic,picmicro,picmaster, picstart, pro mate, seeval and the embedded control solutions company are registered trademarks of microchip tech- nology incorporated in the u.s.a. and other countries. dspic, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, mxdev, picc, picdem, picdem.net, rfpic, select mode and total endurance are trademarks of microchip technology incorporated in the u.s.a. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2002, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
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